Today the Internet comprises over 100 billion plus web pages on over 100 million websites being accessed by nearly 3 billion users conducting approximately 3 billion Google searches per day, sending approximately 150 billion emails per day. With these statistics it is easy to understand but hard to comprehend how much data is being uploaded and downloaded every second on the Internet even before considering the current high growth rate of high bandwidth video. By 2016 this user traffic is expected to exceed 100 exabytes per month, over 100,000,000 terabytes per month, or over 42,000 gigabytes per second. However, peak demand will be considerably higher with projections of over 600 million users streaming Internet high-definition video simultaneously at peak times.
All of this data will flow to and from users via data centers and across telecommunication networks from ultra-long-haul networks down through long-haul networks, metropolitan networks and passive optical networks to users through Internet service providers and then Enterprise/small office—home office (SOHO)/Residential access networks. In the long-haul national and regional backbone networks and metropolitan core networks dense wavelength division multiplexing (DWDM) with channel counts of 40 or 100 wavelengths supporting 10 Gb/s and 40 Gb/s datarates per channel have been deployed over the past decade and are now being augmented with next generation 40 Gb/s and 100 Gb/s coherent technologies for ultra-long-haul, long-haul and metropolitan networks exploiting, for example, polarization multiplexed quadrature phase shift key (PM-QPSK) modulation and soft decision forward error correction (SD-FEC) technology.
In the local area network, within data centers and Ethernet networks generally current and upcoming standards for 100 Gb/s such as 100GBASE-SR10, 100GBASE-SR4, and 100GBASE-LR4 are based upon using 10 lanes of 10 Gb/s or 4 lanes of 25 Gb/s. Traditionally, the strategy for capacity upgrades has been to exploit the benefits of parallel optics and to rely on higher bandwidth availability for the electronic and optical components. However, this approach would require 16 lanes at 25 Gbit/s in order to achieve a 400 Gb/s, thereby making it challenging to meet projected 400 Gbit/s form-factor pluggable, e.g. CDFP2 and CDFP4, requirements on power consumption and footprint. Therefore, it is crucial to develop other solutions for beyond 100 Gbit/s data links satisfying these industry requirements in terms of footprint, power consumption and cost efficiency.
However, already 200 gigabit Ethernet (GbE), 400 GbE, and 1 terabit Ethernet (TbE) are planned using, for example 16×25 Gb/s, 8×50 Gb/s, or 4×100 Gb/s to achieve 400 GbE over singlemode fiber (SMF) for connecting Internet Protocol (IP) core routers and the optical transmission network (OTN) together or connecting IP routers for example. 8×50 Gb/s, or 4×100 Gb/s would be anticipated to be compatible with 400 GbE form-factor pluggable transceivers. At this point in time whilst standards committees such as IEEE 802.3 400 GbE Study Group are developing specifications at multiple link lengths to address these different applications such as 2 km, 10 km, and 40 km there is an overall industry debate as to the modulation format or formats to be employed in the electrical interfaces such as non-return to zero (NRZ), 4-ary pulse amplitude modulation (PAM-4 or PAM4) or other advanced modulation formats. PAM-4 is one example of multilevel amplitude modulation, commonly referred to as M-ary pulse amplitude modulation (PAM-M), along with PAM8 and others.
Today 8×50 Gb/s PAM-4 and 4×100 Gb/s PAM-4 are considered promising candidates to satisfy the 10 km and 2 km SMF objectives respectively in 400 GbE. Discrete multitone modulation (DMT) in conjunction with multi-band carrierless amplitude phase modulation (MCAP) has been proposed for longer distance 40 km SMF links.
Accordingly, in order to exploit optical PAM-4 transmitters it is necessary to establish low cost, small footprint, low power PAM-4 external optical modulators (external modulators) for use in conjunction with optical emitters, such as wavelength stabilised continuous wave (CW) distributed feedback (DFB) laser diodes. Such external optical modulators will exploit photonic integrated circuit (PIC) technologies. Amongst the material technologies for PICs are indium phosphide (the same material system as the DFB laser diodes), lithium niobate, and silicon-on-insulator (SOI). Whilst indium phosphide supports integration of the PAM-4 external modulators it does not support the integration of control and drive electronics. Lithium niobate does not support integration of either the DFB or electronics. However, SOI PICs support monolithic integration of the PIC with the control and drive electronics and hybrid integration of semiconductor DFBs and photodiodes, see for example Kapulainen et al. in “Hybrid Integration of InP Laser with SOI Waveguides using Thermocompression Bonding” (IEEE Conf. Group IV Photonics, pp. 61-63) or semiconductor optical amplifiers, SOI distributed Bragg reflectors, photodetectors and WDM multiplexers/demultiplexer, see for example Alduino et al. in “Demonstration of a High Speed 4-Channel Integrated Silicon Photonics WDM Link with Hybrid Silicon Lasers” (Integrated Photonics Research—Silicon and Nanophotonics, 2010).
As such CMOS compatible SOI photonic integrated circuits (PICs) offer a low cost and promising solution to build future short reach optical links operating beyond 100 Gb/s. A key building block in these optical links is the external optical modulator, which acts as the electro-optic converter encoding the electrical drive derived from the digital data onto the CW optical signal. Amongst, the PIC geometries for external modulators are those based upon ring resonators and Mach-Zehnder interferometers (MZI). Whilst MZI modulators have been reported with increased thermal stability and fabrication tolerances compared to ring resonator modulators, the latter have demonstrated lower loss and good modulation efficiencies at lower peak to peak driving voltages leading to a more energy efficient approach.
Recently, a PAM-4 MZI employing 0.13 μm CMOS technology was reported by Wu et al. operating at data rates over 20 Gb/s, see “A 20 Gb/s NRZ/PAM-4 1V Transmitter in 40 nm CMOS Driving a Si-Photonic Modulator in 0.13 μm CMOS” (2013 IEEE Int. Solid State Circuits Conference, pp. 128-129). The multi-segmented electrode structure based PAM optical modulator can potentially replace the analog digital-to-analog circuits (DACs) which are commonly used to achieve the multilevel electrical driving signal. Accordingly, it would be beneficial to combine the benefits of ring resonators to provide PAM-N modulators. It would be further beneficial for such PAM-N ring resonator modulators to exploit multi-segmented electrode structures to remove the requirements for high speed DACs.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.